DS1642 nonvolatile timekeeping ram DS1642 031698 1/10 features ? integrated nv sram, real time clock, crystal, power fail control circuit and lithium energy source ? standard jedec bytewide 2k x 8 static ram pinout ? clock registers are accessed identical to the static ram. these registers are resident in the eight top ram locations. ? totally nonvolatile with over 10 years of operation in the absence of power ? access times of 120 ns and 150 ns ? quartz accuracy 1 minute a month @ 25 c, factory calibrated ? bcd coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100 ? power fail write protection allows for 10% v cc power supply tolerance pin assignment a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cc a8 a9 we oe a10 ce dq7 dq6 dq5 dq4 dq3 pin description a0a10 address input ce chip enable oe output enable we write enable v cc +5 volts gnd ground dq0dq7 data input/output description the DS1642 is an 2k x 8 nonvolatile static ram with a full function real time clock which are both accessible in a bytewide format. the nonvolatile time keeping ram is pin and function equivalent to any jedec standard 2k x 8 sram. the device can also be easily substituted in rom, eprom and eeprom sockets providing read/ write nonvolatility and the addition of the real time clock function. the real time clock information resides in the eight uppermost ram locations. the rtc registers contain year, month, date, day, hours, minutes, and se- conds data in 24 hour bcd format. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double buffered to avoid access of incorrect data that can occur during clock up- date cycles. the double buffered system also prevents time loss as the timekeeping countdown continues un- abated by access to time register data. the DS1642 also contains its own power fail circuitry which deselects the device when the v cc supply is in an out of tolerance condition. this feature prevents loss of data from un- predictable system operation brought on by low v cc as errant access and update cycles are avoided.
DS1642 031698 2/10 clock operationsreading the clock while the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, the seventh most significant bit in the control register. as long as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock reg- isters of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the DS1642 registers are updated simul- taneously after the clock status is reset. updating is within a second after the read bit is written to zero. DS1642 block diagram figure 1 oscillator and clock countdown chain power monitor, switching, and write protection v cc power good clock registers 2k x 8 nv sram ce we a0a10 dq0dq7 32.768 + oe DS1642 truth table table 1 v cc ce oe we mode dq power 5 volts 10% v ih x x deselect high z standby 5 volts 10% v il x v il write data in active 5 vol ts 10% v il v il v ih read data out active v il v ih v ih read high z active <4.5 volts >v bat x x x deselect high z cmos standby DS1642 031698 3/10 setting the clock the eighth bit of the control register is the write bit. set- ting the write bit to a 1, like the read bit, halts updates to the DS1642 registers. the user can then load them with the correct day, date and time data in 24 hour bcd for- mat. resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb for the seconds registers. setting it to a 1 stops the oscillator. frequency test bit bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic a1o and the oscillator is running, the lsb of the seconds register will toggle at 512 hz. when the seconds register is being read, the dq0 line will toggle at the 512 hz frequency as long as conditions for access remain valid (i.e., ce low, and oe low) and address for seconds register remain valid and stable. clock accuracy the DS1642 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the clock is cali- brated at the factory by dallas semiconductor using special calibration nonvolatile tuning elements. the DS1642 does not require additional calibration and tem- perature deviations will have a negligible effect in most applications. for this reason, methods of field clock cal- ibration are not available and not necessary. attempts to calibrate the clock that may be used with similar de- vice types (mk48t02 family) will not have any effect even though the DS1642 appears to accept calibration data. DS1642 register map bank1 table 2 address data function address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function 7ff year 0099 7fe x x x month 0112 7fd x x date 0131 7fc x ft x x x day 0107 7fb x x hour 0023 7fa x minutes 0059 7f9 osc seconds 0059 7f8 w r x x x x x x control a osc = stop bit r = read bit ft = frequency test w = write bit x = unused note: all indicated axo bits are not dedicated to any particular function and can be used as normal ram bits.
DS1642 031698 4/10 retrieving data from ram or clock the DS1642 is in the read mode whenever we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripplethrough access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the DS1642 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the ad- dresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then dis- able the outputs t wez after we goes active. data retention mode when v cci is within nominal limits (v cc > 4.5 volts) the DS1642 can be accessed as described above by read or write cycles. however, when v cc is below the power fail point v pf (point at which write protection occurs) the internal clock registers and ram is blocked from ac- cess. this is accomplished internally by inhibiting ac- cess via the ce signal. when v cc falls below the level of the internal battery supply, power input is switched from the v cc pin to the internal battery and clock activity, ram, and clock data are maintained from the battery until v cc is returned to nominal level.
DS1642 031698 5/10 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 20 c to +70 c soldering temperature 260 c for 10 seconds (see note 7) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 logic 1 voltage all inputs v ih 2.2 v cc +0.3 v logic 0 voltage all inputs v il 0.3 0.8 v dc electrical characteristics (0 c t a 70 c; v cc (max) v cc v cc (min)) parameter symbol min typ max units notes average v cc power supply current i cc1 30 50 ma 2, 3 ttl standby current (ce = v ih ) i cc2 3 6 ma 2, 3 cmos standby current (ce =v cc 0.2v) i cc3 2 4.0 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v write protection voltage v tp 4.0 4.25 4.5 v
DS1642 031698 6/10 ac electrical characteristics (0 c to 70 c; v cc = 5.0v + 10%) parameter symbol DS1642120 DS1642150 units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns output enable access time t oea 100 120 ns output enable data off time t oez 40 50 ns output enable to dq lowz t oel 5 5 ns ce to dq lowz t cel 5 5 ns output hold from address t oh 5 5 ns write cycle time t wc 120 150 ns address setup time t as 0 0 ns ce pulse width t cew 100 120 ns address hold from end of write t ah1 t ah2 5 30 5 30 ns ns 5 6 write pulse width t wew 75 90 ns we data off time t wez 40 50 ns we or ce inactive time t wr 10 10 ns data setup time t ds 85 110 ns data hold time high t dh1 t dh2 0 25 0 25 ns ns 5 6 ac test conditions input levels: 0v to 3v transition times: 5 ns capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all pins (except dq) c i 7 pf capacitance on dq pins c dq 10 pf
DS1642 031698 7/10 ac electrical characteristics (powerup/down timing) (0 c to 70 c) parameter symbol min typ max units notes ce or we at v ih before power down t pd 0 m s v pf (max) to v pf (min) v cc fall time t f 300 m s v pf (min) to v so v cc fall time t fb 10 m s v so to v pf (min) v cc rise time t rb 1 m s v pf (min) to v pf (max) v cc rise time t r 0 m s power up t rec 15 25 35 ms expected data retention time (oscillator on) t dr 10 years 4 DS1642 read cycle timing t rc t rc t rc read read write t ah t as t wew valid in valid out valid out t oez t aa t oh t cea t cel t oea t oel a0a10 ce oe we dq0dq7 t wr
DS1642 031698 8/10 DS1642 write cycle timing t wc t wc t wc write write read a0a10 ce oe we dq0 valid out valid in valid in valid out t aa t ah1 t oea t wez t as t cew t cez t ds t dh2 t dh1 t ds dq7 t wr t wew t wr t ah2 power down/power up timing v cc t pd t fb ce data retention t dr i batt t f v pf (max) v pf (min) t rec t r t rb v pf v so v so
DS1642 031698 9/10 notes: 1. all voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. data retention time is at 25 c and is calculated from the date code on the device package. the date code xxyy is the year followed by the week of the year in which the device was manufactured. for example, 9225, would mean the 25th week of 1992. 5. t ah1 , t dh1 are measured from we going high. 6. t ah2 , t dh2 are measured from ce going high. 7. realtime clock modules can be successfully processed through conventional wavesoldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. output load +5 volts 100 pf d.u.t. 1.8k w 1k w
DS1642 031698 10/10 DS1642 24pin package 1 c f g k d h b e j a dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.270 37.34 1.290 37.85 0.675 17.15 0.700 17.78 0.315 8.00 0.335 8.51 0.075 1.91 0.105 2.67 0.015 0.38 0.030 0.76 0.140 3.56 0.180 4.57 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.010 0.25 0.018 0.45 0.015 0.43 0.025 0.58 24pin pkg
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